1. Field of Invention
The present invention relates to methods of fabricating integrated circuits. More particularly the use of oriented dummy lines to fill gaps in trace layers prior to a spin-on-glass process is disclosed to improve layer planarity during fabrication.
2. Description of the Prior Art
Maintaining the planarity of a semiconductor wafer surface during fabrication is crucial to insure that there is no accidental coupling of active conductive traces between different layers of active conductive traces on integrated circuits housed on the wafer, and further to provide a surface with a constant height for any subsequent lithography processes. There are many processes which are intended to improve the planarity of a wafer surface during fabrication.
Spin-on glass (SOG) etchback is one process commonly used to improve the planarity of a semiconductor wafer surface during fabrication. In the SOG etchback process, SOG is dispensed at the centerpoint of a semiconductor wafer, which contains a plurality of integrated circuits, while the wafer is rotated in order to spread the SOG as evenly as possible. As a result of its viscosity, SOG flows on the wafer in a weak spiral pattern which can be approximated as a center-to-edge flow pattern. The SOG is intended to fill gaps formed between active metal traces on the surface of the wafer. After the SOG has been deposited, it is etched back to expose portions of at least some of a passivation layer that covers the metal trace layer. The purpose of exposing the passivation layer is to enable a via etch process to take place without vias having to be created through a layer of SOG.
It has been observed that the effectiveness of SOG etchback is dependent on the underlying pattern of metal lines and spaces on the surface of an integrated circuit. SOG easily fills in narrow spaces, but cannot adequately fill in large gaps while maintaining both the nominal thickness of SOG over the portions of the passivation layer which overlay the active conductive traces, and the nominal thickness of SOG on a flat surface away from topography. By way of example, in some existing submicron devices, the SOG over the portions of the passivation layer which overlay the active conductive traces may be in the range of approximately 500-1000 Angstroms while the SOG in areas that do not overlie traces may be on the order of approximately 3000 Angstroms. Thus, while SOG can improve local planarity, i.e. planarity between metal lines which are close in spacing, it is not as efficient in improving global planarity, i.e. planarity between metal lines which are far apart. This leads to problems during optical lithography when the depth of focus is inadequate for surfaces which do not have a consistent height.
FIG. 1 is a diagranmmatic illustration of the surface of a semiconductor wafer having a substrate 10 on which metal lines 12, 14, 16 are situated. A passivation layer 18 is deposited over the metal lines. A layer of SOG 30 is then deposited over the passivation layer. In areas where adjacent metal lines are relatively closely spaced (such as gap 26, which is formed between traces 14 and 16), the gaps between adjacent lines are adequately filled by the SOG 30. However in areas where adjacent metal lines are spaced relatively farther apart (such as gap 28 between traces 12 and 14), indentations 29 tend to be formed in the glass layer 30. Local planarity between metal lines 14 and 16 is improved, while global planarity between metal lines 12 and 14 shows marginal improvement.
While the conventional SOG etchback process is effective in achieving local planarity on the surface of a semiconductor wafer, there is ample room for improvements which can be made to achieve planarity across the entire surface of a semiconductor wafer using the SOG etchback process.